1. Field of the Invention
This invention relates to the field of integrated circuit manufacturing, and in particular to a method for obtaining soft, e.g. phase or transmission, defect information from masks used in the manufacture of integrated circuits. This information can be used to determine the impact of such soft defects on wafer printability.
2. Description of Related Art
In designing an integrated circuit (IC), engineers can use computer simulation tools to help create a circuit design. The circuit design consists of individual devices coupled together to provide certain functions. To fabricate this circuit in a semiconductor substrate on a wafer, the circuit design is translated into a layout. Computer aided design (CAD) tools can assist layout designers in the task of translating the discrete circuit elements (such as gate electrodes, field oxidation regions, diffusion regions, metal interconnections, etc.) into shapes in the layout that implement these circuit elements.
The layout can be transferred onto the semiconductor substrate using optical lithography. Specifically, for each layer of the circuit design, a radiation (e.g. light) source is shone on a mask (or reticle) corresponding to that layer. This radiation passes through clear regions of the mask and is blocked by opaque regions of the mask, thereby selectively exposing a photoresist layer on the wafer. The exposed photoresist layer can then be developed and the semiconductor layer underlying the photoresist can be etched, thereby creating a pattern that defines the shapes of that layer. This process can be repeated for each layer of the circuit design.
One type of mask used in this process, called a binary mask, can be used for less complicated and dense ICs. In more complicated and dense ICs, a binary mask may also include optical proximity correction (OPC) features. Optical proximity correction (OPC) applies systematic changes to the layout to improve the printability of a wafer pattern. Specifically, as the size of IC features drops to 0.18 μ and below, the features can become smaller than the wavelength of the light used to create such features, thereby creating optical distortions when printing the features onto the wafer. These optical distortions can represent significant impacts on device performance.
OPC can include rules to implement certain changes to the layout, thereby compensating for some optical distortions. For example, to compensate for line-end shortening, OPC can add a hammerhead to a line end. Additionally, to compensate for corner rounding, OPC can add (or subtract) serif shapes from outer (or inner) corners. These changes can form features on the wafer that are closer to the original intended layout.
Another advance in lithography, called phase shifting, is able to generate features on the wafer that are smaller than the corresponding wavelength of the exposure radiation. These ultra-small features are generated by the interference of light in adjacent, complementary pairs of phase shifters having opposite phase, e.g. 0 and 180 degrees. In the phase shifting mask (PSM), the complementary phase shifters (also called shifters herein) are configured such that the exposure radiation transmitted by one shifter is 180 degrees out of phase with the exposure radiation transmitted by the other shifter. Therefore, rather than constructively interfering and merging into a single image, the projected images destructively interfere where their edges overlap, thereby creating a clear and very narrow image between the shifters. In one embodiment, the PSM can be used in conjunction with a trim mask, wherein the trim mask can protect the areas exposed by the PSM as well as define other features of the layout. Hence, a lithographic process using a PSM is called a double exposure process.
As circuit designs become more complicated, it becomes increasingly important that the masks used in photolithography can accurately transfer the layout to the wafer. Unfortunately, the machines used to manufacture these masks cannot do so without error. In fact, in a typical manufacturing process, some mask defects do occur outside the controlled process.
A defect on a mask is anything that is different from the circuit design and is deemed unacceptable by an inspection tool or an inspection engineer. The inspection can include scanning the surface of the mask with a high-resolution microscope (e.g. an optical microscope) and capturing images of the mask. If there are no defects, or defects are detected but determined to be within tolerances set by the manufacturer or end-user, then the mask can be used to expose a wafer. However, if defects are detected that fall outside tolerances, then the mask fails the inspection, and a decision must be made as to whether the mask may be cleaned and/or repaired to correct the defects, or whether the defects are so severe that a new mask must be manufactured. This process is continued until a manufactured mask passes the inspection.
However, not all mask defects are important with respect to the desired end result, i.e. an accurate transfer of the layout to the photoresist, which in turn can be etched into a layer of the wafer. In other words, not all mask defects will adversely impact the outcome of a given photolithography and/or etching process. One conventional way to determine the impact of a defect includes exposing an actual wafer. However, a wafer exposure incurs significant costs in time, money, and resource management.
Some currently available tools can advantageously eliminate the need for wafer exposures by using advanced simulation techniques. For example, the Virtual Stepper® system, a mask qualification tool licensed by Numerical Technologies, Inc., can use the optical images generated from an inspection tool to create a simulated image of the final wafer pattern. To perform the simulation, the Virtual Stepper system can use process modeling in which the imaging system wavelength, numerical aperture, coherence factor, illumination modes, reduction factors, and lens aberrations can be considered. Using the simulated wafer image, the Virtual Stepper system can check mask quality and analyze the severity of most mask defects.
However, “soft” defects, e.g. phase and/or transmission defects, on a mask pose unique challenges in both their identification as well as assessing their impact on the printability of the wafer. For example, FIG. 1A illustrates a cross section of a complementary pair of defect-free phase shifters including a 180 degree phase shifter 101 and a 0 degree phase shifter 102. Both shifters are defined by openings provided in a chrome layer 103 formed on a quartz substrate 100. In one embodiment, shifter 101 is formed by performing a 65 degree dry etch in substrate 100 followed by a 115 degree wet etch, thereby providing the desired 180 degree phase shift (i.e. 65+115=180). Note that the dry etch provides a vertical (i.e. an anisotropic) etch into substrate 100, whereas the wet etch provides both a horizontal and vertical (i.e. an isotropic) etch into substrate 100, thereby ensuring that the edges of shifter 101 are under chrome layer 103 to prevent intensity loss. Shifter 102 has no associated etching of substrate 100, thereby providing the desired 0 degree phase shift. FIG. 1B illustrates the complementary pair of phase shifters in FIG. 1A, but including a phase defect 104 in the 180 degree shifter 101. In contrast, FIG. 1C illustrates the complementary pair of phase shifters in FIG. 1A, but including a phase defect 105 in the 0 degree shifter 102.
Identifying the phase of phase defects 104 and 105 could be determined by measuring their physical dimensions. Specifically, by using an extremely accurate measurement tool, such as an atomic force microscope (AFM), the width, length, and depth of each defect could be measured. Using these dimensions as well as the physical properties of substrate 100, e.g. its refractive index, the phase of phase defects 104 and 105 could be computed. Unfortunately, the use of such a measurement tool in a commercial environment is prohibitively expensive.
Therefore, a need arises for a technique to accurately identify soft defects on a mask in a cost effective manner. Moreover, once this soft defect can be identified, a further need arises for a technique to determine the severity of those soft defects on wafer printability.